Such devices are now part of Intel’s portfolio, through Intel’s acquisition of Altera in December 2015. FPGAs are being used to accelerate targeted workloads to enhance the capabilities of general purpose processors. For example, FPGAs are increasingly used in data centers, where accelerating large computing workloads is required to keep the massive amounts of video or large data sets flowing in selected applications. FPGAs are also used in the large service providers’ wireless networks at the base stations, where control and management of services happens. FPGAs will likely play a major role in in the fast-emerging uses around autonomous driving and connecting all the devices of the Internet of Things (IoT), especially as the 5G era commences.
The key value of FPGAs is their programmability, which allows hardware developers designing today’s most innovative electronics to deliver an optimized hardware solution that meet the performance, cost and power requirements for their applications. The possibilities of processors + FPGAs are limited only by the designer’s imagination and ability to innovate.
But this innovation can come at a cost, as hardware and software developers still have to use tools and software to program the FPGA – which requires domain expertise and a learning curve. With traditional RTL methods, programming continues to become more complex as FPGAs and other components evolve, adding more features and performance. Unless developers have moved on to using modern software tools to program the FPGAs, such as the Intel® SDK for OpenCL™ applications, their functional debug iteration times can be frustratingly long. Hence the need for better tools to enable innovation and desired velocity.
Luckily, a new approach is now available to ease the burdens on hardware designers: high level synthesis, or HLS. HLS allows developers or designers to take untimed C++ as input and generate verified RTL that is optimized for the selected device. It’s great for working with Intel FPGAs, and can provide up to 2x the design productivity compared to a traditional RTL design flow.
System Acceleration and Two Times the Design Productivity
Intel® HLS Compiler is a high level synthesis tool that is now in beta and available for RTL designers. With it developers can accelerate time to verified RTL through faster functional verification with Intel FPGA solutions.1 Functional simulations execute up to 1000x faster and design source typically with 80% fewer lines of code that combined can accelerate the overall design process by 2x. The Intel HLS compiler will be offered as part of Intel’s FPGA programming software Quartus, available here.
Intel HLS Compiler is perfect for RTL designers who are implementing transformative algorithms on FPGAs in industries including, but not limited to: wireless, medical, automotive, data center, industrial, and military and aerospace.
Contact your local Intel sales representative to learn more about the Intel HLS Compiler beta program.
1 Benchmark performed using the following hardware and software:
Intel® HLS v. 09, ModelSim-SE-64 10.4d, Hardware 2x8-core Intel Xeon ES 2680 @2.7 GHz, 256 GB RAM
Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, and configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.