If your family is like mine, there are times when everyone is streaming some sort of content, whether it’s TV programs, online videos, or games. We’re consuming broadband bandwidth like never before. To satisfy our voracious appetite for fixed IP traffic, growing at a 21 percent compound annual growth rate¹, cable operators have to deliver higher bandwidth to homes.

Access Network Architecture Options

With the need to increase bandwidth and better optimize the network, network architects are evaluating several variations under the distributed access architecture (DAA) umbrella. DAA shifts where the various functions are performed in the network.² There are generally two main options to choose from in the market: the first known as “Remote PHY” (R-PHY) and the second being “Remote MAC/PHY.” This decision could have a large impact on the total cost of ownership (TCO) with respect to the design, implementation, maintenance, and flexibility of the hardware and software infrastructure.

Testing Capacity & Performance Targets for Virtualized Cable Access Networks

As cable operators consider the available options for network virtualization, they want to be sure the performance and capacity characteristics will match network demand estimates for the foreseeable future.

With this challenge in mind, Intel designed a test environment to measure the potential of virtualized architecture by focusing on DOCSIS MAC data plane running on Intel architecture and the Data Plane Development Kit (DPDK). By establishing an empirical performance data baseline and providing insight into implementation options, we can effectively estimate the capacity of a virtual cable modem termination system (vCMTS) platform running on industry-standard, high-volume servers.

Distributed Access Architecture with Remote PHY or “R-PHY”

The figure below shows a rendition of R-PHY architecture, which is enjoying widespread support throughout the cable operator and vendor community. This approach virtualizes the cable modem termination system (CMTS) along the lines of Network Functions Virtualization (NFV), creating a vCMTS that runs virtual network functions (VNFs).



Figure 1: R-PHY Architecture Example

DOCSIS 3.1 Downstream Pipeline Performance Testing

Helping network architects evaluate the economics of R-PHY, Intel created and tested downstream DOCSIS 3.0 and 3.1 pipelines running on an Intel® Xeon® Scalable processor-based vCMTS to determine the number of high-throughput service groups (SGs) that could be supported. The downstream pipeline is the most performance-critical component on the vCMTS, although the resources consumed by the upstream data path and upstream scheduler must also be accounted for in a platform sizing calculation. The performance testing of both DOCSIS 3.0 and 3.1 is important to assure cable network operators that the current generation of technology can support near-term demand while they invest in next generation networks with DOCSIS 3.1.

Intel engineers found that running a complete DOCSIS 3.1 pipeline on a single processor core was more efficient than partitioning the pipeline across multiple cores. Putting the entire pipeline on a single core was possible partly due to the CPU cycles saved through the use of Data Plane Development Kit (DPDK) APIs. The pipeline, shown in the following figure, also implements containers that allow MAC instantiations at an SG-level of granularity and keep memory footprint to a minimum compared to virtual machines.



Figure 2: The Intel-Developed Downstream Data Plane Pipeline Prototype

Performance Test Results

The DOCSIS 3.1 pipeline throughput was measured for one to 12 SGs, with one processor core dedicated to each SG. An SG supports 300 subscribers, each having five IP addresses. The results are shown in the following figure, which can be used to calculate how many Intel Xeon processor cores are needed for a variety of cable system requirements. The Intel Xeon Scalable processor-based platform delivers performance that scales almost linearly for twelve cores³.



Figure 3: Platform Throughput for Numbers of Service Groups (Software-Only Processing) ³.

Encryption Impacts Bandwidth

To secure data, DOCSIS 3.1 implements Advanced Encryption Standard (AES), a successor to legacy Data Encryption Standard (DES), which is no longer used for new cable deployments; however, DES is used in older versions of DOCSIS, supported by approximately 10 to 20 percent of devices today.

When using software-only encryption to process AES workloads, a hefty 25 percent of the CPU’s cycles were consumed for 1,024 byte packets. Intel engineers were able to more than halve this consumption through the use of Intel® QuickAssist Technology (Intel® QAT). The impact is seen on the following figure, showing a single processor core supporting six channels of orthogonal frequency division multiplexing (OFDM).



Figure 4: Single Processor Core Throughput for Various Packet Sizes 3

Scalability of vCMTS Architecture

The high scalability of vCMTS architecture can be attributed to the relative independence of data plane VNFs running on dedicated processor cores; and thus, more SGs can be handled by spinning up new VNF instances on unused processor cores. When no cores are available, another server can be easily added to the chassis to increase capacity.

Intel plans to use the same test environment and configuration to test upstream pipeline performance of DOCSIS 3.0 and 3.1 technologies in the near future.

To read more about Intel’s vCMTS testing, download the white paper titled, "Maximizing Performance of DOCSIS* 3.0/3.1 Case Study.”

Invest with Confidence. Support DOCSIS Performance into the Next Decade on Intel Architecture

Cable operators are looking for a modicum of certainty that current investments will weather the winds of change. These companies know the pace of innovation or disruption will not slow down, and they want to place a bet on the right technology.

We believe the performance test outlined in this blog and accompanying whitepaper demonstrate that the Intel architecture is ideally suited for flexible, scalable and deterministic DOCSIS MAC processing. The current Intel platform is packed with relevant acceleration features for processing intensive DOCSIS functions, including several security acceleration options for both legacy and new deployments.

The point I want to underscore is that the current Intel architecture and platform can easily serve the demanding performance needs of DOCSIS well into the next decade. While we are confident in the performance of today’s technology, we will continue to invest in enhancements and innovation to ensure the underlying architectural foundation of the cable industry is well-positioned for the next wave of disruption that awaits.