Engagement / Ecosystem Webinars / Optimizing vRAN with Intel® FPGA Platform
Optimizing vRAN with Intel® FPGA Platform
Nadav Yafe, VP Product and Product Marketing and Oren Benisty, VP Sales, Silicom
Feb 15 2022 | 39 mins
- Details
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This webinar will describe the architectural elements, design criteria, technology choices and key chipset employed to build a full layer 1 offload Intel® SmartNIC for a DU in a 4G/5G RAN rollout for any market. With the O-RAN Alliance’s drive to move towards an open ecosystem and interoperable building blocks, Silicom has created an O-RAN standards-compliant Layer 1 High PHY solution over an open, fully programmable platform based on Intel® FPGA, and implemented it as a PCIe add-in card. This webinar aims to demonstrate a design example of this advanced integration and the benefits it can bring to network infrastructure solutions providers.
Presenters:
- Nadav Yafe, VP Product and Product Marketing, Silicom
- Oren Benisty, VP Sales, Silicom
- Intel® Network Builders University
- Intel® Network Builders Newsletter
- Intel® Network Builders Ecosystem Webinars
- Intel® Network Builders Winners’ Circle Program
- Intel® Network Builders University - Radio Access Network (RAN) Overview
- FPGA SmartNIC N6010/6011 Intel based
- PDF of this webinar presentation PDF document 2 MB
- Transcript of this webinar presentation PDF document 230 KB
- Intel® Agilex™ FPGA Architecture White Paper