5G L2 SW Architecture Best Practice on Intel® Architecture
Last Updated: Jan 18, 2019
5G is the next technological revolution. Transformed 5G networks are designed to support a broad range of devices and use cases, with faster speeds, less latency, and more capacity. However, 5G is confronted with many challenges, first of which is TTI (Transmission Time Interval) decreasing from 1ms to 0.125ms while data rate boosting by 10 folds. This demands sharply improved processing capacity of base station, and rigorous real-time performance of software stack. In this context, the architecture design of L2 packet processing, and its implementation and optimization on x86 server platform are vital to fulfilling the 5G throughput and real-time performance target.
Huge throughput demand of 5G brings a great challenge to optimizing locking/ unlocking overhead, and translation lookaside buffer (TLB) miss when multiple tasks/threads get, split or release memory. For MAC/RLC packet processing, Intel adopts DPDK Mempool to buffer management, where the memory is mapped into hugepage. The IA-friendly BBUpooling is also adopted as the framework of FlexRAN L2+ reference library. In this regard, Intel® FlexRAN reference architecture is a solution Intel has offered for the base station.
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