Intel® AVX-512 - Instruction Set for Packet Processing Technology Guide
Last Updated: Feb 24, 2022
This paper is the first in a series of white papers focusing on how to write packet processing software using the AVX-512 instruction set. It provides a brief overview of the Intel® AVX-512 instruction set and describes the microarchitecture optimizations for the instruction set in the latest 3rd Generation Intel® Xeon® Scalable Processors.
Categories
Categories
Software Platforms
NFVI Hardware
NFVI OS/Virtualization
Open Source Solutions
Intel Technologies and Platforms
Intel Atom Processor
2nd gen Intel Xeon Scalable processor
1st gen Intel Xeon Scalable processor
3rd gen Intel Xeon Scalable processor
Network Location
Radio Access Network (RAN)
Hybrid Cloud
Data Center
Device Edge
On Premises
Core Network
Network Technologies
Network Edge
Multi-Access Edge Computing (MEC)
Containers/Kubernetes
Cloud Native/NFV
Next Generation Central Office (NGCO)
Network Security
Optimizations
DPDK
Intel QuickAssist Technology (QAT)
OVS-DPDK
Kubernetes
Enhanced Platform Awareness (EPA)
Verticals/Industries
Financial Services
Industrial
Cloud Service Providers
Manufacturing
Media and Entertainment
Telecommunications
Enterprise
System Integration
VNFS and CNFs
Load Balancer (LB)
Wide Area Network (WAN) Optimization
Firewall (FW)
Broadband Remote Access Server (BRAS)
Session Border Controller (SBC)
IP Multimedia Subsystems (IMS)
Application Delivery Controller (ADC)
Virtualized Radio Access Network (vRAN)
Virtualized Evolved Packet Core (vEPC)
Content Delivery Networks (CDN)
Workloads and Use cases
Smart Cities
Smart Factory
Smart Retail
Video Surveillance
Virtualized Small Cell Gateway
Storage as a Service (SaaS)
SD-WAN and uCPE
Cloud Gaming
Content Distribution (CDN)
Emergency Response
Security
Hide
Related Content
