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Program Overview

The Accelerator program within the Intel® Network Builders University focuses on Intel® technologies that help boost performance while maintaining efficient power consumption.

12 Courses

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In this training you will learn about the basics of the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000.

This course is an introduction to Intel® FPGA Programmable Acceleration Card N3000 (Intel® FPGA PAC) N3000.

In this training you will learn about the foundational concept of Platform Security. It will provide a remote system update (RSU) architecture overview followed by the Accelerator functional Unit (AFU) signing process.

In this training you will learn about the board management controller (BMC) for the Intel® FPGA programmable acceleration card (Intel® FPGA PAC) N3000.

In this training you will learn about building an accelerator functional unit (AFU) for the Intel® FPGA Programmable Acceleration card (Intel® FPGA PAC) N3000.

In this training we will discuss the 5G virtualized Radio Access Network (vRAN) foundational concepts, gain insight into Intel’s vRAN reference design and look at how to compile and design 5G vRAN simulations.

Learn to use the Intel® Quartus® Prime Pro Edition v. 17.1 software to develop an FPGA design from initial design to device programming. This is an online version of a full-day instructor-led training.

Platform Designer, available in the Pro Edition of the Intel® Quartus® Prime software, expands the ease of use, flexibility, and performance of Platform Designer (Standard).

As FPGA designs get larger and more complicated, intellectual property (IP) is often used to help reduce time-to-market. Including IP allows designers to improve existing designs and create new ones. But what if you want to create your own IP?

In this course, you’ll learn about the Fast Preservation feature of the Intel® Quartus Prime Pro edition software and what the advantages are for using it with a block-based design flow. See how to set up a design, use Fast Preservation with that design and see the benefits from using it.

Closing timing can be one of the most difficult and time-consuming aspects of creating an FPGA design. Learn how to perform timing analysis in the Intel® Quartus® Prime software using Timing Analyzer.

Learn how to address timing closure issues with HDL design techniques. This training discusses the problem of timing closure, why it is important to plan for it as well as what to do when you have timing failures in your design.