Accelerators

Program Overview

The Accelerator program within the Intel® Network Builders University focuses on Intel® technologies that help boost performance while maintaining efficient power consumption.

12 Courses

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Introduction to Intel® FPGA Programmable Acceleration Card N3000

(Chapter 1 out of 1)

In this training you will learn about the basics of the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000.

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Getting Started with the Intel® FPGA Programmable Acceleration Card N3000

(Chapter 1 out of 1)

This course is an introduction to Intel® FPGA Programmable Acceleration Card N3000 (Intel® FPGA PAC) N3000.

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Intel® FPGA Programmable Acceleration Card N3000 Security

(Chapter 1 out of 2)

In this training you will learn about the foundational concept of Platform Security. It will provide a remote system update (RSU) architecture overview followed by the Accelerator functional Unit (AFU) signing process.

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Intel® FPGA Programmable Acceleration Card N3000: Board Management Controller

(Chapter 1 out of 1)

In this training you will learn about the board management controller (BMC) for the Intel® FPGA programmable acceleration card (Intel® FPGA PAC) N3000.

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Building an Accelerator Functional Unit for the Intel® FPGA Programmable Acceleration Card N3000

(Chapter 1 out of 1)

In this training you will learn about building an accelerator functional unit (AFU) for the Intel® FPGA Programmable Acceleration card (Intel® FPGA PAC) N3000.

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Chapter 1: 5G Virtualized Radio Access Network (vRAN) Introduction

Intel® FPGA Programmable Acceleration Card N3000 vRAN Reference Design Overview and Usage

(Chapter 1 out of 3)

In this training we will discuss the 5G virtualized Radio Access Network (vRAN) foundational concepts, gain insight into Intel’s vRAN reference design and look at how to compile and design 5G vRAN simulations.

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The Intel® Quartus® Prime Software: Foundation (Pro Edition)

(Chapter 1 out of 1)

Learn to use the Intel® Quartus® Prime Pro Edition v. 17.1 software to develop an FPGA design from initial design to device programming. This is an online version of a full-day instructor-led training.

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Platform Designer in the Intel® Quartus® Prime Pro Edition Software

(Chapter 1 out of 1)

Platform Designer, available in the Pro Edition of the Intel® Quartus® Prime software, expands the ease of use, flexibility, and performance of Platform Designer (Standard).

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Chapter 1: Introduction to IP Reuse with the Intel® Quartus® Prime Software

Creating Reusable Design Blocks with Intel® Quartus® Prime Software

(Chapter 1 out of 3)

As FPGA designs get larger and more complicated, intellectual property (IP) is often used to help reduce time-to-market. Including IP allows designers to improve existing designs and create new ones. But what if you want to create your own IP?

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Reducing Compile Time with Fast Preservation

(Chapter 1 out of 1)

In this course, you’ll learn about the Fast Preservation feature of the Intel® Quartus Prime Pro edition software and what the advantages are for using it with a block-based design flow. See how to set up a design, use Fast Preservation with that design and see the benefits from using it.

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Chapter 1: Timing Analyzer: Introduction to Timing Analysis

Timing Analysis using Intel® Quartus® Prime Software

(Chapter 1 out of 2)

Closing timing can be one of the most difficult and time-consuming aspects of creating an FPGA design. Learn how to perform timing analysis in the Intel® Quartus® Prime software using Timing Analyzer.

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Best Practices for Timing Closure

(Chapter 1 out of 2)

Learn how to address timing closure issues with HDL design techniques. This training discusses the problem of timing closure, why it is important to plan for it as well as what to do when you have timing failures in your design.

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