The Accelerator program within the Intel® Network Builders University focuses on Intel® technologies that help boost performance while maintaining efficient power consumption.
Best Practices for Timing Closure (2 Chapters)
Learn how to address timing closure issues with HDL design techniques. This training discusses the problem of timing closure, why it is important to plan for it as well as what to do when you have timing failures in your design.
Timing Analysis using Intel® Quartus® Prime Software (2 Chapters)
Closing timing can be one of the most difficult and time-consuming aspects of creating an FPGA design. Learn how to perform timing analysis in the Intel® Quartus® Prime software using Timing Analyzer.
Platform Designer, available in the Pro Edition of the Intel® Quartus® Prime software, expands the ease of use, flexibility, and performance of Platform Designer (Standard).
In this training we will discuss the 5G virtualized Radio Access Network (vRAN) foundational concepts, gain insight into Intel’s vRAN reference design and look at how to compile and design 5G vRAN simulations.
In this training you will learn about the foundational concept of Platform Security. It will provide a remote system update (RSU) architecture overview followed by the Accelerator functional Unit (AFU) signing process.