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Accelerators

Program Overview

The Accelerator program within the Intel® Network Builders University focuses on Intel® technologies that help boost performance while maintaining efficient power consumption.

13 Courses

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Introduction to Intel® FPGA Programmable Acceleration Card N3000 (1 Chapters)

Chapter 1: Introduction to Intel® FPGA Programmable Acceleration Card N3000

OVERVIEW

In this training you will learn about the basics of the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000.

Watch Chapter 1 out of 1

Getting Started with the Intel® FPGA Programmable Acceleration Card N3000 (1 Chapters)

Chapter 1: Getting Started with the Intel® FPGA Programmable Acceleration Card N3000

OVERVIEW

This course is an introduction to Intel® FPGA Programmable Acceleration Card N3000 (Intel® FPGA PAC) N3000.

Watch Chapter 1 out of 1

Intel® FPGA Programmable Acceleration Card N3000 Security (2 Chapters)

Chapter 1: Intel® FPGA Programmable Acceleration Card N3000 Security

OVERVIEW

In this training you will learn about the foundational concept of Platform Security. It will provide a remote system update (RSU) architecture overview followed by the Accelerator functional Unit (AFU) signing process.

Watch Chapter 1 out of 2

Intel® FPGA Programmable Acceleration Card N3000: Board Management Controller (1 Chapters)

Chapter 1: Intel® FPGA Programmable Acceleration Card N3000 Board Management Controller

OVERVIEW

In this training you will learn about the board management controller (BMC) for the Intel® FPGA programmable acceleration card (Intel® FPGA PAC) N3000.

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Building an Accelerator Functional Unit for the Intel® FPGA Programmable Acceleration Card N3000 (1 Chapters)

Chapter 1: Building an Accelerator Functional Unit for the Intel® FPGA Programmable Acceleration Card N3000

OVERVIEW

In this training you will learn about building an accelerator functional unit (AFU) for the Intel® FPGA Programmable Acceleration card (Intel® FPGA PAC) N3000.

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Intel® FPGA Programmable Acceleration Card N3000 vRAN Reference Design Overview and Usage (3 Chapters)

Chapter 1: 5G Virtualized Radio Access Network (vRAN) Introduction

OVERVIEW

In this training we will discuss the 5G virtualized Radio Access Network (vRAN) foundational concepts, gain insight into Intel’s vRAN reference design and look at how to compile and design 5G vRAN simulations.

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The Intel® Quartus® Prime Software: Foundation (Pro Edition) (1 Chapters)

Chapter 1: The Intel® Quartus® Prime Software: Foundation (Pro Edition)

OVERVIEW

Learn to use the Intel® Quartus® Prime Pro Edition v. 17.1 software to develop an FPGA design from initial design to device programming. This is an online version of a full-day instructor-led training.

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Platform Designer in the Intel® Quartus® Prime Pro Edition Software (1 Chapters)

Chapter 1: Platform Designer in the Intel® Quartus® Prime Pro Edition Software

OVERVIEW

Platform Designer, available in the Pro Edition of the Intel® Quartus® Prime software, expands the ease of use, flexibility, and performance of Platform Designer (Standard).

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Creating Reusable Design Blocks with Intel® Quartus® Prime Software (2 Chapters)

Chapter 1: Introduction to IP Reuse with the Intel® Quartus® Prime Software

OVERVIEW

As FPGA designs get larger and more complicated, intellectual property (IP) is often used to help reduce time-to-market. Including IP allows designers to improve existing designs and create new ones. But what if you want to create your own IP?

Watch Chapter 1 out of 2

Reducing Compile Time with Fast Preservation (1 Chapters)

Chapter 1: Reducing Compile Time with Fast Preservation

OVERVIEW

In this course, you’ll learn about the Fast Preservation feature of the Intel® Quartus Prime Pro edition software and what the advantages are for using it with a block-based design flow. See how to set up a design, use Fast Preservation with that design and see the benefits from using it.

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Timing Analysis using Intel® Quartus® Prime Software (2 Chapters)

Chapter 1: Timing Analyzer: Introduction to Timing Analysis

OVERVIEW

Closing timing can be one of the most difficult and time-consuming aspects of creating an FPGA design. Learn how to perform timing analysis in the Intel® Quartus® Prime software using Timing Analyzer.

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Best Practices for Timing Closure (2 Chapters)

Chapter 1: Best Practices for Timing Closure

OVERVIEW

Learn how to address timing closure issues with HDL design techniques. This training discusses the problem of timing closure, why it is important to plan for it as well as what to do when you have timing failures in your design.

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Augmenting F5’s BIG-IP VE with SmartNICs to Improve DDoS Protection in Virtualized Environments (1 Chapters)

Chapter 1: Augmenting F5’s BIG-IP VE with SmartNICs to Improve DDoS Protection in Virtualized Environments

OVERVIEW

F5’s BIG-IP Virtual Edition (VE) for SmartNICs integrates F5’s BIG-IP VE with an Intel® FPGA PAC N3000. Learn how DDoS mitigation is offloaded to the FPGA-based smartNIC to defend against attacks in virtual environments while reducing TCO.

Watch Chapter 1 out of 1